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FEATURES 10-Bit, 18 MSPS A/D Converter 18 MSPS Full-Speed CDS Low Noise, Wideband PGA Internal Voltage Reference No Missing Codes Guaranteed +3 V Single Supply Operation Low Power CMOS: 185 mW 48-Pin TQFP Package
PBLK
19
CCD Signal Processor For Electronic Cameras AD9801
FUNCTIONAL BLOCK DIAGRAM
CLPDM
23
PGACONT1 PGACONT2
29 30
SHP SHD ADCCLK
21 22 16
CLAMP PIN 27 CDS DIN 26 CLAMP REFERENCE
37 48 47 18 20 33
TIMING GENERATOR PGA S/H A/D 10
2
DOUT
11
AD9801
43 17
12
DRVDD
CMLEVEL VRT VRB STBY
CLPOB
ACVDD
ADVDD
DVDD
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9801 is a complete CCD signal processor developed for electronic cameras. It is well suited for both video conferencing and consumer level still camera applications. The signal processing chain is comprised of a high speed CDS, variable gain PGA and 10-bit ADC. Required clamping circuitry and an onboard voltage reference are also provided. The AD9801 operates from a single +3 V supply with a typical power consumption of 185 mW. The AD9801 is packaged in a space saving 48-pin thin-quad flatpack (TQFP) and is specified over an operating temperature range of 0C to +70C.
1. On-Chip Input Clamp and CDS Clamp circuitry and high speed correlated double sampler allow for simple ac coupling to interface a CCD sensor at full 18 MSPS conversion rate. 2. On-Chip PGA The AD9801 includes a low noise, wideband amplifier with analog variable gain from 0 dB to 31.5 dB (linear in dB). 3. 10-Bit, High Speed A/D Converter A linear 10-bit ADC is capable of digitizing CCD signals at the full 18 MSPS conversion rate. (Typical DNL is 0.5 LSB and no missing code performance is guaranteed.) 4. Low Power At 185 mW, the AD9801 consumes a fraction of the power of presently available multichip solutions. The part's powerdown mode (15 mW) further enhances its desirability in low power, battery operated applications. 5. Digital I/O Functionality The AD9801 offers three-state digital output control. 6. Small Package Packaged in a 48-pin, surface-mount thin-quad flatpack, the AD9801 is well suited to very tight, low headroom designs.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD9801-SPECIFICATIONS otherwise noted)
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) ACVDD ADVDD DVDD DRVDD POWER SUPPLY CURRENT ACVDD ADVDD DVDD DRVDD POWER CONSUMPTION Normal Operation Power-Down Mode MAXIMUM SHP, SHD, ADCCLK RATE ADC Resolution Differential Nonlinearity No Missing Codes ADCCLK Rate Reference Top Voltage Reference Bottom Voltage Input Range CDS Maximum Input Signal Pixel Rate PGA1 Maximum Gain High Gain Medium Gain Minimum Gain CLAMP Average Black Level (During CLPOB. Only Stable Over PGA Range 0.3 V to 2.7 V)
1
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless
Min 0 -65 Typ Max 70 150 Units C C
3.00 3.00 3.00 3.00
3.15 3.15 3.15 3.15 39.5 14.6 4.7 0.07 185 15
3.50 3.50 3.50 3.50
V V V V mA mA mA mA mW mW MHz Bits LSB
18 10
0.5 GUARANTEED 18 1.75 1.25 1.0
MHz V V V p-p mV p-p MHz dB dB dB dB
500 18 31.5 19 3.5 -1
15 0.5 -5
23 6.5 +3
32
LSB
PGA test conditions: max gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 = 0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (T
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage
MIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)
Symbol VIH VIL IIH IIL CIN VOH VOL IOH IOL
Min 2.4
Typ
Max
Units V V A A pF V V A A
0.6 10 10 10 2.4 0.6 50 50
Specifications subject to change without notice.
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AD9801 TIMING SPECIFICATIONS (T
Parameter ADCCLK CLOCK PERIOD ADCCLK High Level Period ADCCLK Low Level Period SHP, SHD Clock Period Digital Output Delay
MIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)
Min 55.6 24.8 24.8 55.6
Typ 27.8 27.8 20
Max
Units ns ns ns ns ns
Digital Output Data Control
Mode1 0 0 1 1
Mode2 0 1 0 1
Digital Output Data (D9-D0) Normal Operation 10 101 01 010 High Impedance 0 1 1 0 0 1 1 0 0 1
ABSOLUTE MAXIMUM RATINGS*
Parameter ADVDD ACVDD DVDD DRVDD SHP, SHD ADCCLK, CLOB, CLPDM PGACONT1, PGACONT2 PIN, DIN DOUT VRT, VRB CLAMP_BIAS CCDBYP1, CCDBYP2 STBY MODE1, MODE2 DRVSS, DVSS, ACVSS, ADVSS Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect To ADVSS, SUBST ACVSS, SUBST DVSS, DSUBST DRVSS, DSUBST DSUBST DSUBST SUBST SUBST DSUBST SUBST SUBST SUBST DSUBST SUBST SUBST, DSUBST
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65
Max 6.5 6.5 6.5 6.5 DVDD + 2.0 DVDD + 0.3 ACVDD + 0.3 ACVDD + 0.3 DRVDD + 0.3 ADVDD + 0.3 ACVDD + 0.3 ACVDD + 0.3 DVDD + 0.3 ADVDD + 0.3 +0.3 +150 +150 +300
Units V V V V V V V V V V V V V V V C C C
* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Model AD9801
Temperature 0C to +70C
Package Description 48-Pin TQFP
Package Option* ST-48
*ST = Thin Quad Flatpack Package.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9801 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9801
PIN CONFIGURATION
CLAMP_BIAS PGACONT2 PGACONT1 INT_BIAS1 CCDBYP1 CCDBYP2
24 DVSS 23 CLPDM 22 SHD 21 SHP 20 CLPOB 19 PBLK 18 STBY 17 DVDD 16 ADCCLK 15 DVSS PIN 1 IDENTIFIER 14 DSUBST 13 DRVSS 1 2 3 4 5 6 7 8 9 10 11 12
ACVDD
ACVDD
ACVDD
ACVSS
36 35 34 33 32 31 30 29 28 27 26 25
CMLEVEL 37 INT_BIAS2 38 MODE2 39 MODE1 40 ADVSS 41 ADVDD 42 ADVDD 43 ADVSS 44 ADVSS 45 SUBST 46 VRB 47 VRT 48
AD9801
TOP VIEW (Not to Scale)
ADVSS
D1
D2
D3
D4
PIN D8
(MSB) D9
(LSB) D0
D7
DIN
Pin No. 1 2-11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Name ADVSS D0-D9 DRVDD DRVSS DSUBST DVSS ADCCLK DVDD STBY PBLK CLPOB SHP SHD CLPDM DVSS CCDBYP2 DIN PIN CCDBYP1 PGACONT1 PGACONT2 ACVSS CLAMP_BIAS ACVDD ACVDD ACVDD INT_BIAS1 CMLEVEL INT_BIAS2 MODE2 MODE1 ADVSS ADVDD ADVDD ADVSS ADVSS SUBST VRB VRT
Type P DO P P P P DI P DI DI DI DI DI DI DI AO AI AI AO AI AI P AO P AI AI AO AO AO DI DI P P P P P P AO AO
Description Analog Ground Digital Data Outputs +3 V Digital Driver Supply Digital Driver Ground Digital Substrate Digital Ground ADC Sample Clock Input +3 V Digital Supply Power down (Active HIGH) Pixel Blanking (Active LOW) Black Level Restore Clamp (Active LOW) Reference Sample Clock Input Data Sample Clock Input Input Clamp (Active Low) Digital Ground CCD Bypass (Decouple to Analog Ground Through 0.1 F) CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1 F) CDS Input (See Above) CCD Bypass (Decouple to Analog Ground Through 0.1 F) Coarse PGA Gain Control (0.3 V-2.7 V Decoupled to Analog Ground Through 0.1 F) Fine PGA Gain Control (0.3 V-2.7 V Decoupled to Analog Ground Through 0.1 F) Analog Ground Clamp Bias Level (Decouple to Analog Ground Through 0.1 F) +3 V Analog Supply +3 V Analog Supply +3 V Analog Supply Internal Bias Level (Decouple to Analog Ground Through 0.1 F) Common-Mode Level (Decouple to Analog Ground Through 0.1 F) Internal Bias Level (Decouple to Analog Ground Through 0.1 F) ADC Test Mode Control (See Digital Output Data Control) ADC Test Mode Control (See Digital Output Data Control) Analog Ground +3 V Analog Supply +3 V Analog Supply Analog Ground Analog Ground Substrate (Connect to Analog Ground) Bottom Reference Bypass (Decouple to Analog Ground Through 0.1 F) Top Reference Bypass (Decouple to Analog Ground Through 0.1 F) -4- REV. 0
DRVDD
D5
D6
AD9801
EQUIVALENT INPUT CIRCUITS
DVDD DRVDD
ACVDD
50 10pF
SUBST ACVSS
Figure 6. Pin 26 (DIN) and Pin 27 (PIN)
DVSS
DRVSS
ACVDD 10k PGACONT1
Figure 1. Pins 2-11 (DB0-DB9)
SUBST PGACONT2 8k ACVDD
DVDD
1k
8k
200
Figure 7. Pin 29 (PGACONT1) and Pin 30 (PGACONT2)
ACVSS
DSUBST
DVSS
10k 50 5.25k 30k SUBST ACVSS
Figure 2. Pin 21 (SHP) and Pin 22 (SHD)
DVDD ADVDD
200 9.3k ADVSS
Figure 8. Pin 32 (CLAMP BIAS)
DSUBST
DVSS
Figure 3. Pin 16 (ADCCLK)
Figure 4. Pin 37 (CMLEVEL)
ACVDD
ACVDD
200
SUBST
ADVSS
Figure 9. Pin 48 (VRT) and Pin 47 (VRB)
SUBST
DVSS
Figure 5. Pin 25 (CCDBYP2) and Pin 28 (CCDBYP1)
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AD9801
EFFECTIVE PIXEL INTERVAL BLACK LEVEL INTERVAL BLANKING INTERVAL DUMMY BLACK INTERVAL EFFECTIVE PIXEL INTERVAL
CCD
SHP
SHD
CLPOB
PBLK
CLPDM
ADCCLK
ADC DATA
NOTE: CLPDM OVERWRITES PBLK CLAMP TIMING NEEDS TO BE ADJUSTED RELATIVE TO CCD'S BLACK PIXELS
Figure 10. Typical Horizontal Interval Timing
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AD9801
1
CCD SIGNAL (DELAYED TO MATCH ACTUAL SAMPLING EDGE)
2
3
4
5
6
7
N N+1
N+2 N+3
N+4
SHD
SHP ACTUAL SAMPLING EDGE 35ns ADCCLK 35ns
tID
tOD
DIGITAL OUT
tH
DATA N-1 DATA N
OUTPUT LOAD CL = 20pF
OUTPUT DELAY tOD = 15ns HOLD TIME tH = 2ns INTERNAL CLOCK DELAY tHD = 3ns LATENCY = 5 CYCLES
Figure 11. Timing Diagram
SHP
SHD
PRE-ADC OUTPUT LATCH
5ns 10ns
PRE-ADC OUTPUT LATCH DATA TRANSITION 5ns ADCCLK 15ns INHIBITED PERIOD FOR ADCCLK TO CHANGE RISING EDGE ANYWHERE IN THIS PERIOD OK
Figure 12. ADCCLK Timing Edge
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AD9801
THEORY OF OPERATION Introduction
35 30 25 20
GAIN - dB
The AD9801 is a 10-bit analog-to-digital interface for CCD cameras. The block level diagram of the system is shown in Figure 13. The device includes a correlated double sampler (CDS), 0 dB-31 dB variable gain amplifier (PGA), black level correction loop, input clamp and voltage reference. The only external analog circuitry required at the system level is an emitter follower buffer between the CCD output and AD9801 inputs.
CLAMP BLACK LEVEL CDS PGA 10b ADC OUT
15 10 5 0 -5
-10 -15 0 0.5 1 1.5 2 PGACONT1 - Volts 2.5 3
IN
GAIN
REF
Figure 15.
Figure 13.
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a method for removing several types of noise. Basically, two samples of the CCD output are taken: one with the signal present ("data") and one without ("reference"). Subtracting these two samples removes any noise that is common--or correlated--to both. Figure 14 shows the block diagram of the AD9801's CDS. The S/H blocks are directly driven by the input and the sampling function is performed passively, without the use of amplifiers.
S/H FROM CCD S OUT
As shown in Figure 16, PGA control is provided through the PGACONT1 and PGACONT2 inputs. PGACONT1 provides coarse and PGACONT2 fine (1/16) gain control.
PGACONT1 PGACONT2
A PGACONT1 = COURSE CONTROL PGACONT2 = FINE CONTROL (1/16)
Figure 16.
Black Level Clamping
Q1 S/H
Q2 10pF
For correct processing, the CCD signal must be referenced to a well established "black level" by the AD9801. At the edge of the CCD, there is a collection of pixels that are covered with metal to prevent any light penetration. As the CCD is read out, these "black pixels" provide a calibration signal that is used to establish the black level. The feedback loop shown in Figure 17 is closed around the PGA during the calibration interval (CLPOB = LOW) to set the black level. As the black pixels are being processed, an integrator block measures the difference between the input level and the desired reference level. This difference, or error, signal is amplified and passed to the CDS block where it is added to the incoming pixel data. As a result of this process, the black pixels are digitized at one end of the ADC range, taking maximum advantage of the available linear range of the system.
IN CDS
Figure 14.
This implementation relies on the off-chip emitter follower buffer to drive the two 10 pF sampling capacitors. Only one capacitor at a time is seen at the input pin. The AD9801 actually uses two CDS circuits in a "ping pong" fashion to allow the system more acquisition time. In this way, the output from one of the two CDS blocks will be valid for an entire clock cycle. Thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a single CDS channel system. This lower bandwidth translates to lower power and noise.
Programmable Gain Amplifier (PGA)
PGA
ADC CLPOB
INTEGRATOR
NEG REF
The on-chip PGA provides a (linear in dB) gain range of 0 dB-31.5 dB. A typical gain characteristic plot is shown in Figure 15. Only the range from 0.3 V to 2.7 V is intended for actual use.
Figure 17.
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AD9801
The actual implementation of this loop is slightly more complicated as shown in Figure 18. Because there are two separate CDS blocks, two black level feedback loops are required and two offset voltages are developed. Figure 18 also shows an additional PGA block in the feedback loop labeled "RPGA."
CDS1 IN CDS1 CLPOB RPGA2 RPGA1 INT2 INT1 PGA ADC
To avoid problems associated with processing these transients, the AD9801 includes an input blanking function. When active (PBLK = LOW), this function stops the CDS operation and allows the user to disconnect the CDS inputs from the CCD buffer. If the input voltage exceeds the supply rail by more than 0.3 V, protection diodes will be turned on, increasing current flow into the AD9801 (see Equivalent Input Circuits). Such voltage levels should be externally clamped to prevent device damage or reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
NEG REF
CONTROL
Figure 18.
The RPGA uses the same control inputs as the PGA, but has the inverse gain. The RPGA functions to attenuate by the same factor as the PGA amplifies, keeping the gain and bandwidth of the loop constant.
Input Bias Level Clamping
The ADC employs a multibit pipelined architecture, which is well-suited for high throughput rates while being both area and power efficient. The multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. A fully differential implementation was used to overcome headroom constraints of the single +3 V power supply.
Differential Reference
The buffered CCD output is connected to the AD9801 through an external coupling capacitor. The dc bias point for this coupling capacitor is established during the clamping (CLPDM = LOW) period using the "dummy clamp" loop shown in Figure 19. When closed around the CDS, this loop establishes the desired DC bias point on the coupling capacitor.
CLPDM INPUT CLAMP CCD CDS PGA TO ADC
The AD9801 includes a 0.5 V reference based on a differential, continuous-time bandgap cell. Use of an external bypass capacitor reduces the reference drive requirements, thus lowering the power dissipation. The differential architecture was chosen for its ability to reject supply and substrate noise. Recommended decoupling shown in Figure 20.
VRT REF VRB 1F 0.1F 0.1F
Figure 20.
Internal Timing
BLACK LEVEL CLP
Figure 19.
Input Blanking
The AD9801's on-chip timing circuitry generates all clocks necessary for operation of the CDS and ADC blocks. The user needs only to synchronize the SHP and SHD clocks with the CCD waveform, as all other timing is handled internally. The ADCCLK signal is used to strobe the output data, and can be adjusted to accommodate desired timing.
In some applications, the AD9801's input may be exposed to large signals from the CCD. These signals can be very large, relative to the AD9801's input range, and could thus saturate on-chip circuit blocks. Recovery time from such saturation conditions could be substantial.
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AD9801
APPLICATION INFORMATION Generating Clock Signals
For best performance, the AD9801 should be driven by 3 V logic levels. As shown in the Equivalent Input Circuits, the use of 5 V logic for ADCCLK will turn on the protection diode to DVDD, increasing the current flow into this pin. As a result, noise and power dissipation will increase. The CDS clock inputs, SHP and SHD, have additional protection and can withstand direct 5 V levels. External clamping diodes or resistor dividers can be used to translate 5 V levels to 3 V levels, but the lowest power dissipation is achieved with a logic transceiver chip. National Semiconductor's 74LVX4245 provides a 5 V to 3 V level shift for up to eight clock signals, and features a three-state option and low power consumption. Philips Semiconductor and Quality also manufacture similar devices.
Digitally Programmable Gain Control
1 2 +3V PGACONT2 1F 5 6 7 SHDN CS 3 4
14 13 12 +3V PGACONT1 0.1F +3V 1F
AD8402-10
11 10 9 8 SDI CLK RS
Figure 21. Digital Control of PGA
reference may be used. The REF193 from Analog Devices features low power, low dropout performance, maintaining a 3 V output with a minimum 3.1 V supply when lightly loaded.
Power and Grounding Recommendations
The AD9801's PGA is controlled by an analog input voltage of 0.3 V to 2.7 V. In some applications, digital gain control is preferable. Figure 21 shows a circuit using Analog Devices' AD8402 Digital Potentiometer to generate the PGA control voltage. The AD8402 functions as two individual potentiometers, with a serial digital interface to program the position of each wiper over 256 positions. The device will operate with 3 V or 5 V supplies, and features a power-down mode and a reset function. To keep external components to a minimum, the ends of the "potentiometers" can be tied to ground and +3 V. One pot is used for the coarse gain adjust, PGACONT1, with steps of about 0.2 dB/LSB. The other pot is used for fine gain control, PGACONT2, and is capable of around 0.01 dB steps if all eight bits are used. The two outputs should be filtered with 1 F or larger capacitors to minimize noise into the PGACONT pins of the AD9801. The disadvantage of this circuit is that the control voltage will be supply dependent. If additional precision is required, an external op amp can be used to amplify the VREFT (1.75 V) or VREFB (1.25 V) pins on the AD9801 to the desired voltage level. These reference voltages are stable over the operating supply range of the AD9801. Low power, low cost, rail-to-rail output amplifiers such as the AD820, OP150 and OP196 are specified for 3 V operation. Alternatively, a precision voltage
The AD9801 should be treated as an analog component when used in a system. The same power supply and ground plane should be used for all of the pins. In a two-ground system, this requires that the digital supply pins be decoupled to the analog ground plane and the digital ground pins be connected to analog ground for best noise performance. If any pins on the AD9801 are connected to the system digital ground, noise can capacitively couple inside the AD9801 (through package and die parasitics) from the digital circuitry to the analog circuitry. Separate digital supplies can be used, particularly if slightly different driver supplies are needed, but the digital power pins should still be decoupled to the same point as the digital ground pins (analog ground plane). If the AD9801 digital outputs need to drive a bus or substantial load, a buffer should be used at the AD9801's outputs, with the buffer referenced to system digital ground. In some cases, when system digital noise is not substantial, it is acceptable to split the ground pins on the AD9801 to separate analog and digital ground planes. If this is done, be sure to connect the ground pins together at the AD9801. To further improve performance, isolating the driver supply DRVDD from DVDD with a ferrite bead can help reduce kickback effects during major code transitions. Alternatively, the use of damping resistors on the digital outputs will reduce the output risetimes, reducing the kickback effect.
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AD9801
EVALUATION BOARD
Figure 22 shows the schematic for the AD9801 evaluation board. Notice the use of a common ground and supply for the AD9801, and the extensive supply and reference decoupling.
AVCC AVCC CW R6 10k
3 7
AVCC AVCC TP25 CW R7 10k PGACONT1 C70 10F 16V R15 68
3 7
C56 0.1F C37 0.1F
2
C49 0.01F
C52 0.1F C36 0.1F
2
C54 0.01F TP24
U6
AD707
4
6
U7
AD707
4
6
PGACONT2 C71 10F 16V
R14 68
C50 0.1F AVSS
C55 0.01F
C51 0.1F AVSS
C57 0.01F
VDD PIN C61 0.1F C7 0.1F C12 0.1F C9 2F C10 2F C11 0.1F PGACONT1 PGACONT2 VDD JP3 1k CW JP2 JP1 DIN
36 35 34 33 32 31 30 29 28 27 26 25
0.1F
C8 0.1F TP5 DVSS 24 CLPDM 23 SHD 22 SHP 21 CLPOB 20 STBY
INT_BIAS1 ACVDD
PGACONT1
CCDBYP1
CLAMP_BIAS
PGACONT2
CCDBYP2
ACVSS
ACVDD
ACVDD
DIN
PIN
C23 0.1F
JP4
C6 0.1F
37 38
C5 0.1F VDD
CMLEVEL INT_BIAS2 39 MODE2 MODE1 ADVSS ADVDD ADVDD ADVSS ADVSS SUBST VRB VRT
CLPDM SHD SHP CLPOB PBLK
40 41 42 43
U1
AD9801
PBLK 19 STBY 18 DVDD 17 ADCCLK 16 DVSS 15 DSUBST 14 DRVSS 13
C4 0.1F
44 45 46 47
ADCCLK VDD
D9 (MSB) DRVDD
D0 (LSB)
ADVSS
C2 0.1F
C1 1F
48
C13 0.1F
C29 0.01F 40 PIN HEADER
D1
D3 D4
D5
D2
D6
D7
C3 0.1F
D8
1
2
3
4
5
6
7
8
9
10 11 12
C14 0.1F
FB4 VDD +3V JP1 C46 0.1F TP27 FB2 C45 0.1F C44 22F C67 0.1F AVCC JP5 FB1 TP28 C47 22F C66 0.1F VDD JP3 -5V
C28 0.01F
FB3 C40 0.1F
TP26 C41 22F C68 0.1F AVSS
+5V JP2
GND
TP29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
D0
D1
D3
D4
D2
D5
D7
D6
D8
D9
ADCCLK
Figure 22. AD9801EB Schematic
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AD9801
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Terminal Plastic Thin Quad Flatpack (ST-48)
0.354 (9.00) BSC 0.276 (7.0) BSC
48 1 37 36
0.030 (0.75) 0.018 (0.45)
0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
SEATING PLANE TOP VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05) 0 - 7
0 MIN 0.007 (0.18) 0.004 (0.09)
12 13
25 24
0.019 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
0.354 (9.00) BSC
0.276 (7.0) BSC
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PRINTED IN U.S.A.
C2975-12-1/97
0.063 (1.60) MAX

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